A clock and data recovery (CDR) loop is used to recover an embedded clock from an incoming serial data stream. Conventionally this requires that the frequency of a locally generated clock signal (the “recovered clock”) be close to the fundamental frequency of the data stream (i.e., the frequency corresponding to the bit rate). This can be difficult for non-return-to-zero (NRZ) coded data streams, because there is generally no energy at the fundamental data frequency. NRZ streams do not have a rest state that signifies a transition.
Referring to FIG. 1, in a conventional structure 100 that includes a phase locked (PLL) loop and is used for serial data stream clock and data recovery, a reference clock signal from a reference clock 101 is generated at about the fundamental frequency of serial data stream 110. Reference clock 101 is generally local to loop 100 and is used with frequency detector 130 to initially pull-in the PLL. Frequency detector 130 and a phase detector 120 are used with the PLL to generate a signal tuned to match the incoming data. Once lock is achieved, control of the loop frequency is done by phase detector 120 (e.g., an Alexander or Hogge style phase detector), which generally tracks transitions in the incoming data stream.
The need for the reference clock at the data fundamental frequency adds to the system cost and complexity. It is therefore desirable to have a frequency adjustment mechanism, which does not require such a clock.
Returning now to FIG. 1, phase detector 120 of loop 100 will generally lock to the incoming data stream if the frequency of variable frequency oscillator (VFO) 170 is sufficiently close to the fundamental frequency of data stream 110. Therefore, any auxiliary frequency adjustment mechanism (e.g., reference clock 101 and frequency detector 130) need not result in an exact frequency lock, but rather just bring the recovered clock close to the data stream's fundamental frequency.
Some fundamental frequency energy can be extracted from the serial data input stream 110 by differentiating and squaring the signal. FIG. 2 shows a conventional implementation of a circuit 200 configured to perform such a process to generate an output 240. Serial data input stream 210 may be coupled to both one input of exclusive-or (XOR) element 230 and to digital delay element 220. The output of delay element 220 may be coupled to the second input of XOR 230. In the conventional approach, the delay value of element 220 should be very small to get close to ideal differentiation.
FIG. 3 shows a conventional frequency detector. This detector compares the frequency of the reference input to the frequency of the in-phase and quadrature local clock using the conventional rotational detection algorithm. This detector advantageously decreases the rate of correction pulses as the two frequencies come closer together. However, it has the disadvantage that missing pulses on one of the inputs may distort the output pulses (e.g., UP/DOWN in FIG. 1) by lengthening them for the duration of the missing pulse.
In view of the foregoing problems with conventional clock and data recovery loops, the present invention provides improvements in this area of technology.